To address efficiency needs, the portfolio includes an advanced design differencing engine that enables design review with global teams using state of art visuals. The OrCAD portfolio also features enhancements targeted towards improving PCB editors' productivity and ease-of-use in padstack editing, constraint management, shape editing and in-design DRCs.
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To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD portfolio uses a new multi-stack-up database capability and extensive in-design inter-layer checks, which helps users avoid errors introduced through manual checking. OrCAD is the only fully scalable PCB design solution available in the market that seamlessly transitions from mainstream to enterprise PCB solution with the Allegro environment. This enables hardware/software virtual prototyping so that electrical engineers can design and simulate intelligent IoT devices. PSpice Designer now supports system-level simulation using C/C++/SystemC and VerilogA, via the new PSpice compact model interface. This OrCAD portfolio includes new advanced technology enabled for integrated rigid-flex planning, design and real-time visualization, as well as built-in translators that enable direct design imports from select EDA vendors. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
pxml file issue: thermal data is not importedĢ195724 ALLEGRO_EDITOR SHAPE Via Array boundary gives error (SPMHA1-507): PolyBool has hit an assertĢ199694 ALLEGRO_EDITOR SHAPE Board crashes with Shape updateĢ201630 ALLEGRO_EDITOR SHAPE Board crashes when updating bottom layer shape after deleting shape islandsĢ168018 ALLEGRO_PROD_TOOLB CORE PCB Design Compare - Limit check to outline extents only functionalityĢ172272 ALLEGRO_PROD_TOOLB CORE Placing a module in Fab panelization gives error message regarding handling nilĢ163792 ALTM_TRANSLATOR PCB_EDITOR Third-party translator translating symbol names incorrectlyĢ136023 APD BGA_GENERATOR 'add connect' does not snap to the BGA pins for padstacks other than SMDĢ200707 APD PADSTACK_EDIT Pad Editor cannot save the pad and cannot close it.Ģ203680 CAPTURE NETLIST_ALLEG Netlisting displays errors but the log file is emptyĢ104576 CONCEPT_HDL CORE Validating physical part information for components in design - DE-HDL stops responding for 2 minutesĢ197754 CONCEPT_HDL CORE Note command results in alignment issue due to spaces added to the end of wordsĢ164539 CONCEPT_HDL CREFER Crefer missing when instance and part names are sameĢ195341 CONCEPT_HDL CREFER Crefer treats all notes as left-justified in release 17.2-2016, HotFix 061Ģ191513 CONCEPT_HDL OTHER net_spacing_type cannot be deleted from netsĢ195275 PULSE R2PLM Stale BOM is published unless BOM refresh icon is clickedĢ195018 SCM SETUP Adding PINUSE column to CCP crashes SCMĢ186309 SIP_LAYOUT DEGASSING Degassing does not add voids to the entire shapeĬadence Design Systems announced new capabilities for OrCAD Capture, PSpice Designer and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables and wireless mobile devices. , the leader in global electronic design innovation, has unveiled a new of improvements to the Cadence SPB Allegro and OrCAD 17.20 families of products aimed at boosting performance and productivity through improvements features and big fixed issues.Ģ180529 ADW DBEDITOR Unable to release a part - For logical part, pack type is present in chips.prt but missing in ptfĢ181458 ADW DBEDITOR dbeditor - old version retained when using Copy-asĢ191531 ALLEGRO_EDITOR DATABASE Export libraries cannot export packageĢ167426 ALLEGRO_EDITOR DRAFTING The diameter symbol is in front of the measurements instead of being behindĢ184335 ALLEGRO_EDITOR EDIT_ETCH PCB Editor stops responding when routing an arc by using the 'Connect' commandĢ199429 ALLEGRO_EDITOR EDIT_ETCH PCB Editor stops responding when routing a clineĢ204713 ALLEGRO_EDITOR EDIT_ETCH Lag in commands when working with board in release 17.2-2016 and 16.6Ģ203244 ALLEGRO_EDITOR MULTI_USER Symphony team design error with intermittent crash on refreshing DBĢ177214 ALLEGRO_EDITOR PAD_EDITOR Import/Export.
Cadence SPB Allegro and OrCAD 17.20.000-2016 HF064 | 3.9 GbĬadence Design Systems, Inc.
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